(1) Field of the Invention
The present invention relates to a method of manufacturing a master-slice integrated circuit device, and more particularly to a method of designing circuit patterns, i.e., the mask patterns for master-slice integrated circuit devices such as a gate array LSI device. The circuit patterns are designed from a block circuit diagram by using logic blocks, each of which includes a plurality of basic logic blocks.
(2) Description of the Prior Art
The mask patterns for a gate-array LSI device are made from a logic circuit designed by the customer using basic logic blocks, such as basic cells in a logic block family, consisting of various gate circuits and the like. Information on the logic block family is supplied to the customer by the LSI manufacturer. In certain cases, such as when many different kinds of gate array LSI's are manufactured, circuits with structures partially common to each other are often used. In such cases, it is generally possible to define a common portion that includes a plurality of basic logic blocks as a logic block such as, for example, a macro cell, and to thereby simplify the design work of the gate array LSI's.
In conventional methods for manufacturing master-slice integrated circuit devices, however, since it is impossible to use part of the basic logic blocks forming a logic block, it has been necessary to define logic blocks as different logic blocks even when the circuits of the logic blocks differ only slightly from each other. For example, when it is necessary to use counter circuits having different bit numbers, such as two-bit counters, three-bit counters, four-bit counters, and so on, separate logic blocks have to be defined for all counters having different bit numbers. In this type of method, therefore, the number of different kinds of logic blocks becomes relatively large. Because many libraries of these logic blocks must be registered in a computer, the memory capacity of the computer has to be enlarged, the processing time for computational processes in design automation (DA) extended, and the memory capacity of the working areas enlarged. Moreover, artificial errors increase when the libraries of the logic blocks are registered in the computer, in addition to which the reliability of the gate array LSI's deteriorates.